The embodiments described herein are related to electronic design automation tools, and more particularly to calculating timing characteristics (e.g., output delay and slew) of a circuit while modeling variations in circuit parameters, such as a voltage supply, temperature, and process parameters.
One aspect of integrated circuit design involves determining timing parameters and power consumption to characterize the chip. Currently, large scale integration (“LSI”) designs are transitioning from deep submicron to ultra deep submicron (“DSM/UDSM”) feature sizes. With this transition, timing and power verification becomes more critical to achieve high electrical performance with complex integrated circuit designs. In addition to feature sizes, the accuracy of timing and power verification is also critical due to the ever-increasing size of integrated circuit designs. Furthermore, fast and accurate power and timing verification techniques are critical to meet the time to market product window demands on today's integrated circuit designs.
In general, the timing parameters define how signals propagate from one section of the chip to another. For example, timing parameters define rising signal and falling signal propagation times from driver circuits to receiver circuits in large scale integration (“LSI”) circuits. Currently, timing and power information is generated based on instance-based delay and power calculation. The delay and power calculation is formulated from a fixed library. Specifically, the library defines the pin-to-pin delay and output rise and fall times from a fixed reference lookup table of input signal slew rates and output loading capacitances. Using a fixed base library, output rise and fall times are specified based on input signal slew rates and fixed output loading capacitances.
Using conventional methods to generate a library for timing verification, a load capacitance and input signal slew rate are used to derive the change of output voltage from the change of input voltage. However, this simple technique does not account for circuit level and device level non-linear characteristics. To further simplify the analytical requirements, the output signal curve is specified as a linear sweep. With the continuing rapid advances in lithography, and as transistor dimensions become smaller, this output signal curve is dominated to a much larger extent by the transistors' nonlinear region of operation. Operation of the transistors in the nonlinear region is a result of the transistor switching speed in CMOS circuits.
This technique causes errors in computing both the driving instance delay and the RC network propagation delay. Specifically, these linear sweep techniques cannot match actual signal curves and thus introduce unacceptable error for the delay calculation. In addition, resistive shielding effects are also not properly handled with the linear sweep technique. The resistive shielding effects are caused by the resistive element in the RC network. Using these techniques, the actual signal delay may be significantly different then the delay predictions. Accordingly, related U.S. Pat. No. 6,721,929 entitled “High Accuracy Timing Model for Integrated Circuit Verification” which is hereby incorporated by reference as if fully set forth herein, discloses a new driving methodology that properly calculates delay and power results to accurately reflect the nonlinear behavior particularly found in DSM/UDSM designs.
Another aspect of integrated circuit design involves accommodating changes in circuit parameters such as supply voltage, temperature, and process. For example, in the case of varying supply voltage, instances of the same cell may be used in different parts of a circuit with different supply voltages. The same circuit may be used for different functions depending on a particular application, and thus, require a different supply voltage or a range of supply voltages. Thus the circuit response to each value in supply voltage range must be analyzed. Process represents a collection of parameters including oxide thickness (tox), threshold voltage (Vt), transistor width (W), and transistor length (L). Each value of process is associated with a particular set of parameter values, one value for each parameter in the collection.
There is a need in circuit design to efficiently model timing characteristics of a cell when the cell must accommodate one or more circuit parameters that can vary within a given range. For the purposes of explanation, this description will use the embodiment of supply voltage variation and the embodiment of simultaneous variation of supply voltage and temperature as examples.
The conventional method of modeling supply voltage variation on delay is Linear Derating of the delay based on the supply voltage. Historically, delay at a given supply voltage is calculated by multiplying the known delay at a pre-characterized voltage by a constant “K-factor”, as shown in the following equation:delay(V2)=delay(V1)*(1+K(V2−V1))The V1 voltage is the operating condition at which the delay table in the library file is characterized. The K-factor must have been characterized in the library for the calculation to be effective. Linear derating of delay with supply voltage can lead to inaccuracies in the calculated delay as the supply voltage is decreased.
Another approach for modeling supply voltage variation would be to use the circuit characterization model found in U.S. Pat. No. 6,721,929 for each supply voltage value in the range. Disclosed in U.S. Pat. No. 6,721,929 is a variable current source model that accurately determines timing delays for designs of circuits implemented in integrated circuits. A design for an integrated circuit specifies a resistive-capacitive (“RC”) network, such as a wiring network that interconnects circuits in an integrated circuit. The RC network couples a driving point and a receiving point. A circuit specified in the design, such as a gate level circuit implemented in a standard cell, drives the RC network at the driving point. The variable current source model determines driving currents for the circuit at the driving point based on the RC network and a characterization of the circuit. A timing delay between the driving point and the receiving point is determined by simulating the drive of the RC network with the driving current at the driving point. A circuit characterization model is generated to determine, for each time instance, a new drive current from the drive voltage and the load capacitance from a prior time instance. The circuit characterization model depicts relationships among input signal slew rates, load capacitances, drive currents, and drive voltages for the circuit in the form of a characterization library. Each element in the characterization library stores an eleven element array for each slew and load capacitance parameters of the cell. Each array stores the output delay value and ten points on the output waveform.
A library of characterization data for each voltage value in the range would be stored for every cell. While this approach would be accurate, it needlessly burdens the memory requirements of a system and would require every cell to be characterized for every supply voltage value it could be operated under. A more accurate and efficient method of modeling voltage variation for delay calculation with variation in circuit parameters is needed.